In a synchronous digital system, different components of the system are synchronized by means of a clock signal. A clock signal is a succession of high and low values. Typically, the high values are provided by a high voltage level while the low values are provided by a low voltage level. The clock signal is typically periodic, both for the sake of simplicity and to maximize the number of operations per second performed by the synchronous circuit. The clock signal can take the form of a square wave, a sinusoidal wave, a succession of pulses, or any other function which oscillates between a low value (low) and a high value (high). Transitions in the clock signal from low to high and from high to low are termed rising edges and falling edges, respectively. The components of the synchronous digital system may be triggered by only rising edges, or only falling edges, or by both rising edges and falling edges. The period of the clock signal and its inverse are referred to, respectively, as the clock period and the clock frequency. The clock period and the clock frequency may be measured in, e.g., seconds and Hertz, respectively. The time between a rising edge and the subsequent falling edge, divided by the clock period, is known as the duty cycle of the clock signal. In the case of a synchronous system which utilizes both rising and falling edges of the clock signal, the duty cycle must be neither too small nor too large. Typically, the duty cycle is desired to be approximately 50%. In the case where the clock signal is not a square wave, the rising edges and the falling edges can be defined, for example, by referring to the instants at which the value of the clock signal is the average of its low value and its high value when the clock signal passes from a low to a high or from a high to a low, respectively.
An available clock signal does not necessarily have the desired duty cycle. For example, a clock may generate a clock signal having a duty cycle of 30% which is adapted for the majority of components of the synchronous system, while one component of the system requires a duty cycle of 50%. In another example, a clock signal having originally a duty cycle of 50% is transmitted over a clock tree. Components of the clock tree may affect the quality of the clock signal such that the duty cycle of the clock signal delivered to a particular component of the synchronous digital system has a duty cycle different from 50%. In both cases, a clock signal having a desired duty cycle of 50% can be recovered from the original clock signal by means of a duty cycle corrector. The duty cycle corrector receives the original clock signal (input clock signal) and generates from it an output signal having the same frequency as the input clock signal and having the desired duty cycle.
Referring to FIGS. 1 to 4, there are illustrated a method and a circuit for generating from an input clock signal an output clock signal having a desired duty cycle, according to the prior art. Both the input clock signal CLKIN and the output clock signal CLK_50 are provided in the form of a voltage V which periodically oscillates between a low value and a high value as a function of time t. During an interval of length T1 the input clock signal CLKIN is high. During an interval of length T2 the input clock signal CLKIN is low. The clock period is T=T1+T2. The duty cycle of the input clock signal CLKIN is T1/T.
Referring now specifically to FIG. 1, the duty cycle T1/T of the input clock signal is 20%. The output clock signal CLK_50 is generated from the input clock signal CLKIN by transmitting rising edges with essentially no delay while delaying falling edges by 30% of the clock period T. The output clock signal CLK_50 thus has a duty cycle T1′/T of 50% as desired. The delay by which falling edges of the input clock signal CLKIN are delayed may of course be adjusted in this manner so as to obtain a duty cycle of the output clock signal CLK_50 having any desired value.
Referring now specifically to FIG. 2, the duty cycle of the input clock signal CLKIN is T1/T=80%. An output clock signal CLK_50 having a duty cycle T1′/T of 50% is generated from CLKIN by delaying rising edges of CLKIN while transmitting falling edges with essentially no delay. The rising edges of the output clock signal CLK_50 thus generated are seen to be delayed with respect to the corresponding rising edges of the input clock signal CLKIN by a duration Δt which in the present example is 30% of the clock period T. This delay Δt depends on the difference between the duty cycle of the input clock signal and the desired duty cycle. In this sense, the output clock signal CLK_50 has an unspecified delay Δt with respect to the input clock signal CLKIN. This can be problematic in a synchronous digital system, where it is usually required that rising edges at different points of a clock tree occur simultaneously. In other words, the output clock signal CLK_50 has an undetermined phase relative to the input clock signal CLKIN.
Huang et al., in “Low-Power 50% Duty Cycle Corrector” circuit and systems, 2008, pages 2362 to 2365 (2008), have presented a duty cycle corrector for implementing the method described above with reference to FIGS. 1 and 2. That duty cycle corrector is briefly described with reference to FIG. 3. The duty cycle corrector 10 comprises a control stage 14, 16, 18, 20, 22, 24 with input at node 12 and output at node 26, a buffer chain 28, 30, 32 with input at node 26 and output at node 34, a duty cycle detector 36, 38, 40, 42, 44, 46, 48 with input at node 34 and output at node 58, and a feedback path 50 from node 58 to the gate of a PMOS transistor 18 and an NMOS transistor 20 of the control stage. The control stage 14, 16, 18, 20, 22, 24 is essentially a CMOS inverter comprising the PMOS transistor 14 and the NMOS transistor 16, wherein the source of PMOS transistor 14 is coupled via a PMOS transistor 18 to a high bias potential 22 while NMOS transistor 16 is coupled to a low bias potential 24 via an NMOS transistor 20. If transistors 18 and 20 where perfectly conductive, the control stage would simply invert the clock signal CLKIN received at node 12 to deliver an inverted clock signal at node 26, by converting high into low, and low into high. However, transistors 18 and 20 are controlled by means of control voltage VCTL generated at the capacitor 40 by the duty cycle detector. The higher VCTL, the higher will be the conductivity of NMOS transistor 20 and the lower will be the conductivity of PMOS transistor 18. Conversely, the lower VCTL, the higher will be the conductivity of PMOS transistor 18 and the lower will be the conductivity of NMOS transistor 20. Thus, by varying VCTL, the rise time and the fall time of the control stage 12, 14, 16, 20, 26 can be controlled. More specifically, the higher VCTL, the faster a high-to-low transition at node 26 and the slower a low-to-high transition at node 26 will be. Conversely, the lower VCTL, the faster a low-to-high transition and the slower a high-to-low transition will be. Depending on the value of VCTL, the control stage thus delays predominantly either rising edges or falling edges of the input clock signal CLKIN to produce a raw output clock signal CLKR. If the input clock signal CLKIN is a square wave, the raw output clock signal CLKR is not. A square wave signal CLK_50 is recovered from CLKR by passing the latter through the chain of buffers 28, 30, 32.
The duty cycle detector comprises the capacitor 40, a first current source 36, a second current source 38, a PMOS transistor 42 coupled to the first current source 36, and an NMOS 44 transistor coupled to the second current source 38. It is coupled between a high bias potential 46 and a low bias potential 48 and operates as follows. When the potential at node 34, i.e. the output of the buffer chain 28, 30, 32, is high, NMOS transistor 44 but not PMOS transistor 42 is conductive and the second current source 38 lowers the voltage at the capacitor 40. Conversely, when the potential at node 34 is low, PMOS transistor 42 but not NMOS transistor 44 is conductive and the first current source 36 increases the voltage at capacitor 40. When the duty cycle of the output clock signal CLK_50 is 50%, the voltage at capacitor 40 will remain constant when averaged over one clock period.
The control stage, the buffer chain, the duty cycle detector, and the feedback path 50 together form a closed loop causing the control voltage VCTL to converge to an average value such that the output clock signal CLK_50 assumes a duty cycle of 50%. A duty cycle different from 50% could be achieved by, for example, using current sources 36, 38 producing currents I1 and I2 respectively, such that T1×I1=T2×I2 where T1 and T2 are the durations of the high and the low in the desired output signal, respectively.
Illustrated in FIG. 4 is an output clock signal CLKOUT obtained from an input clock signal CLKIN using a prior art duty cycle corrector as shown in FIG. 3. In plot (a), (b), and (c), the duty cycle of the input clock signal CLKIN is 80%, 50%, and 20%, respectively. In plot (a) the output clock signal CLKOUT is retarded relative to the input clock signal CLKIN by 30% of the clock period.